The invention relates to copper interconnects, and more particularly to copper interconnects including a low-k inter-metal dielectric (IMD) layer and a low-k etching stop (ES) layer.
As the density of semiconductor devices increases and the size of circuit elements becomes smaller to achieve better performance, resistance capacitance (RC) delay time in back-end-of-line (BEOL) increases and dominates circuit performance. To reduce RC delay time in BEOL, the demands on interconnects for connecting semiconductor devices to each other also increase. Copper interconnection has been adapted to silicon integrated circuits due to its low resistance and high electromigration reliability compared to traditional aluminum interconnection. Also, low-k dielectrics of dielectric constant (k) less than 3.5 have been used as inter-metal dielectrics (IMDs) for replacing traditional silicon-dioxide-based dielectrics.
Currently, single-damascene and dual-damascene methods are employed in copper interconnect processes. For patterning copper dual damascene interconnects (DDIs), a thin dielectric layer with high dielectric constant (k>4.5) is required to function as a via/trench etch stop (ES) layer and a copper diffusion/oxidation barrier. Such a high-k ES layer integrated with low-k IMD layers, however, results in a substantially increased dielectric constant of the combined dielectric layers. Consequently, when electric currents are conducted through the copper interconnects, a large parasitic capacitance would occur in the low-k IMD layer. This parasitic capacitance will then cause an increased RC delay to the signals being transmitted through the copper interconnects, thus degrading the performance of the IC device.
In order to meet RC delay requirements, a porous low-k material of a smaller dielectric constant (k<2.5), such as organo-silicate glass (OSG), has been employed as the IMD layer and integrated with the high-k ES layer in the copper dual damascene process. One drawback, however, is that the porous low-k material has weak mechanical properties, including low film hardness (less than 0.2 GPa) and low elastic modulus (less than 5 GPa), causing high process cost, high process risk, and poor reliability.
In addition, the conventional ES structure is a single layer with a high etching selectivity to the IMD layer in order to protect the underlying copper layer from oxidation due to moisture and exposure to air. The via etching process, however, easily breaks through the single-layer ES structure due to variation in IMD thickness, isolation/dense pattern effect, micro-loading effect and feature size reduction. This causes the ES structure failure and damages to the underlying copper layer in subsequent etching/ashing processes, thus degrading uniformity and reliability of the copper interconnection.